From 3f5f74d1349625fa33bcbdfd2956d1e36b3f236d Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 28 Jan 2020 19:53:01 -0800 Subject: mb/intel/tglrvp: pin mux for ISH TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable, PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c. Pin mux for ISH for TGLRVP ISHUART0: GPP_D13, GPP_D14 as NF1 ISHI2C0: GPP_B5, GPP_B6 as NF1 ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux. Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting. They should be NF1. Signed-off-by: Wonkyu Kim Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/mainboard/intel/tglrvp/variants') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index d1dc4ca251..8638b806b6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -32,6 +32,24 @@ static const struct pad_config gpio_table[] = { /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + + /* ISH UART0 RX/TX */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + + /* ISH I2C0 */ + PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + + /* ISH GPI 0-6 */ + PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ -- cgit v1.2.3