From 3c8cb24fc32d0322da5cfd7fabae3b66ac16470b Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 19 May 2020 20:21:00 -0700 Subject: mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvp This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from tglrvp devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on tglrvp. Signed-off-by: John Zhao Change-Id: I3b77fe15bd67e513f193f704030a98241e058437 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41554 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 ++++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src/mainboard/intel/tglrvp/variants') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 045dc89e4d..24cc907da7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -109,6 +109,10 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 83b6c0ae0c..eb6814e5bf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -105,6 +105,10 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoPci, }" + # D3Hot and D3Cold for TCSS + register "TcssD3HotEnable" = "1" + register "TcssD3ColdEnable" = "1" + # TCSS USB3 register "TcssAuxOri" = "0" -- cgit v1.2.3