From 7e303581bcda7d7a4a90d75a9b6f6698d55287ce Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 6 Mar 2020 14:36:23 -0800 Subject: mb/intel/tglrvp: Add TGL UP4 RVP Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363 Reviewed-by: Nick Vaccaro Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up4/memory.c | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c new file mode 100644 index 0000000000..67979b649b --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_lpddr4x_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ + 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ + { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ + 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ + { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ + 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ + { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ + 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ + { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ + 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ + { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ + 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ + { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ + 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ + { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ + 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} -- cgit v1.2.3