From b449b9c182943696075363d25845a91229615e8c Mon Sep 17 00:00:00 2001
From: Shaunak Saha <shaunak.saha@intel.com>
Date: Sun, 23 Aug 2020 21:35:21 -0700
Subject: mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Cq-Depend:chromium-review:1881839
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
---
 .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 23 ++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

(limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb')

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index ad7eabe158..384bc1bb6e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -9,8 +9,8 @@ chip soc/intel/tigerlake
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
 	register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
-	register "pmc_gpe0_dw2" = "GPP_E"
+	register "pmc_gpe0_dw1" = "GPP_C"
+	register "pmc_gpe0_dw2" = "GPP_D"
 
 	# Enable heci1 communication
 	register "HeciEnabled" = "1"
@@ -86,14 +86,14 @@ chip soc/intel/tigerlake
 
 	register "SerialIoGSpiMode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 	}"
 
 	register "SerialIoGSpiCsMode" = "{
 		[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
 		[PchSerialIoIndexGSPI2] = 0,
 		[PchSerialIoIndexGSPI3] = 0,
 	}"
@@ -152,6 +152,10 @@ chip soc/intel/tigerlake
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
 		.i2c[0] = {
 			.speed = I2C_SPEED_FAST,
 		},
@@ -294,8 +298,15 @@ chip soc/intel/tigerlake
 		device pci 1d.3 off end # RP12			0xA0B3
 		device pci 1e.0 off end # UART0			0xA0A8
 		device pci 1e.1 off end # UART1			0xA0A9
-		device pci 1e.2 off end # GSPI0			0xA0AA
-		device pci 1e.3 off end # GSPI1			0xA0AB
+		device pci 1e.2 on end # GSPI0			0xA0AA
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1					0xA0AB
 		device pci 1f.0 on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
-- 
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