From fdba0cd6af05f9317dbd19956d644ce01e37a547 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 19 Feb 2020 00:48:55 -0800 Subject: mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc index 23bf160883..c272607042 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2019-2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -15,4 +15,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c -- cgit v1.2.3