From fdba0cd6af05f9317dbd19956d644ce01e37a547 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 19 Feb 2020 00:48:55 -0800 Subject: mb/intel/tglrvp: add Tiger Lake memory initialization support Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik --- src/mainboard/intel/tglrvp/romstage_fsp_params.c | 50 ++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) (limited to 'src/mainboard/intel/tglrvp/romstage_fsp_params.c') diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 0ab1f48fee..89ae0ab3fb 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,11 +12,55 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include +#include #include #include +#include +#include +#include +#include +#include +#include "board_id.h" +#include "spd/spd.h" + +static uintptr_t mainboard_get_spd_index(void) +{ + uint8_t board_id = (get_board_id() & 0xFF); + int spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + switch (board_id) { + case TGL_U_LP4_MICRON: + spd_index = SPD_ID_MICRON; + break; + case TGL_U_LP4_SAMSUNG: + spd_index = SPD_ID_SAMSUNG; + break; + case TGL_U_LP4_HYNIX: + spd_index = SPD_ID_HYNIX; + break; + default: + spd_index = SPD_ID_MICRON; + printk(BIOS_WARNING, "Invalid board_id 0x%x\n", board_id); + } + + printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index); + return spd_index; +} void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + const struct mb_lpddr4x_cfg *mem_config = variant_memory_params(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = mainboard_get_spd_index(), + }; + bool half_populated = false; + + meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated); + } -- cgit v1.2.3