From 9900cf80091ad1796c78c04b6ef6302410444480 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Fri, 6 Mar 2020 16:46:39 -0800 Subject: mb/intel/tglrvp: Add memory config for Tiger Lake UP4 Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/board_id.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/mainboard/intel/tglrvp/board_id.h') diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 364f4f7b04..8d0a31751b 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -22,9 +22,14 @@ #define EC_FAB_ID_CMD 0x0D /* TGL-U Board IDs */ -#define TGL_U_LP4_SAMSUNG 0x3 -#define TGL_U_LP4_HYNIX 0xB -#define TGL_U_LP4_MICRON 0x13 +#define TGL_UP3_LP4_SAMSUNG 0x3 +#define TGL_UP3_LP4_HYNIX 0xB +#define TGL_UP3_LP4_MICRON 0x13 + +/* TGL-Y Board IDs */ +#define TGL_UP4_LP4_SAMSUNG 0x5 +#define TGL_UP4_LP4_HYNIX 0xD +#define TGL_UP4_LP4_MICRON 0x15 /* * Returns board information (board id[15:8] and -- cgit v1.2.3