From b0f81518b5c17466bc95ebdef292e82c4b76bc88 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 25 Jul 2016 21:31:41 -0500 Subject: chromeos mainboards: remove chromeos.asl Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie --- src/mainboard/intel/strago/acpi/chromeos.asl | 33 ---------------------------- src/mainboard/intel/strago/chromeos.c | 10 +++++++++ src/mainboard/intel/strago/dsdt.asl | 1 - src/mainboard/intel/strago/mainboard.c | 2 ++ 4 files changed, 12 insertions(+), 34 deletions(-) delete mode 100644 src/mainboard/intel/strago/acpi/chromeos.asl (limited to 'src/mainboard/intel/strago') diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl deleted file mode 100644 index c470ca3e9d..0000000000 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: We need to encode gpios within the 4 separate banks - * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. - */ - -Name(OIPG, Package() { - /* No physical recovery button */ - Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10013, "Braswell" }, -}) diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 0e072f0dc0..0fb98111a8 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -118,3 +118,13 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index f1248d8d7c..59af6ddb95 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include } } - #include "acpi/chromeos.asl" #include /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 0566c8e2f6..71ba62b13e 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "ec.h" static void mainboard_init(device_t dev) @@ -32,6 +33,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } -- cgit v1.2.3