From c1c1ba5582fa0302476491c46f18cc73b69c88ac Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 20 Apr 2021 16:57:59 -0700 Subject: soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/shadowmountain/variants/baseboard/devicetree.cb | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/mainboard/intel/shadowmountain/variants') diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 9464f10fe0..b06e540b84 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -111,13 +111,6 @@ chip soc/intel/alderlake # HD Audio register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "0" - register "PchHdaAudioLinkDmicEnable[1]" = "0" - register "PchHdaAudioLinkSspEnable[0]" = "0" - register "PchHdaAudioLinkSspEnable[1]" = "0" - register "PchHdaAudioLinkSndwEnable[0]" = "0" - register "PchHdaAudioLinkSndwEnable[1]" = "0" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "3" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. -- cgit v1.2.3