From 1b150cb000a189f7564486ec9411222718374111 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Fri, 15 Jan 2021 14:01:54 +0530 Subject: mb/intel/shadowmountain: Add bootblock and verstage code This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aamir Bohra --- .../shadowmountain/variants/baseboard/early_gpio.c | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c (limited to 'src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c') diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c new file mode 100644 index 0000000000..29e6184447 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* A7 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A17 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A19 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_A19, NONE, DEEP), + /* A20 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_A20, NONE, DEEP), + /* B11 : PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT), + + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), + + /* F14 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F20 : WWAN_RST_ODL + To meet timing constraints - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} -- cgit v1.2.3