From ce07b5c0ab304b2f13bbebd731dd1a8fc1077446 Mon Sep 17 00:00:00 2001
From: V Sowmya <v.sowmya@intel.com>
Date: Thu, 17 Dec 2020 08:03:03 +0530
Subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board

This patch adds initial support for Alderlake Intel Pre-CEP
board called shadowmountain.

BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max

Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/intel/shadowmountain/dsdt.asl | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 src/mainboard/intel/shadowmountain/dsdt.asl

(limited to 'src/mainboard/intel/shadowmountain/dsdt.asl')

diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
new file mode 100644
index 0000000000..10d08e26e2
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+}
-- 
cgit v1.2.3