From ce07b5c0ab304b2f13bbebd731dd1a8fc1077446 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 17 Dec 2020 08:03:03 +0530 Subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/shadowmountain/board_info.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/mainboard/intel/shadowmountain/board_info.txt (limited to 'src/mainboard/intel/shadowmountain/board_info.txt') diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt new file mode 100644 index 0000000000..7e0cccf015 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake Pre-CEP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y -- cgit v1.2.3