From 8cb7af8e7c139afd982cea54e579870ee089e4c7 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Tue, 23 Feb 2021 13:31:34 +0530 Subject: mb/intel/shadowmountain: Enable Type-C subsystem This patch adds the changes to enable the TCSS. BUG=b:175808146 TEST= Boot shadowmountain board, Test the functionality of the Type-C ports on both the mainboard and daughterboard by plugging in the Type-C devices and verified the devices are detected via EC console and in the OS. Signed-off-by: V Sowmya Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026 Reviewed-by: Angel Pons Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/mainboard/intel/shadowmountain/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/mainboard/intel/shadowmountain/Kconfig') diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 6a5abc160d..2dbd653e0d 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC @@ -19,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE config CHROMEOS @@ -54,4 +56,16 @@ config MAINBOARD_PART_NUMBER string default "shadowmountain" +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + endif # BOARD_INTEL_SHADOWMOUNTAIN -- cgit v1.2.3