From 88bc0f1604494de0f87c6954c050e7ef4d1c4457 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 8 Jul 2024 04:29:39 +0200 Subject: skl/kbl mainboards: Move PCIe related settings into their device scope Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Matt DeVillier Reviewed-by: Erik van den Bogaert Reviewed-by: Jonathon Hall --- src/mainboard/intel/saddlebrook/devicetree.cb | 44 +++++++++++++-------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'src/mainboard/intel/saddlebrook') diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index c92377a149..968e2a666b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -98,28 +98,6 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - # Enable x1 slot - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - - # Enable x4 slot - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[12]" = "1" - - # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[5]" = "0" - register "PcieRpClkReqNumber[12]" = "1" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -207,6 +185,28 @@ chip soc/intel/skylake device ref i2c5 on end device ref i2c4 on end device ref pcie_rp1 on end + device ref pcie_rp6 on + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "0" + end + device ref pcie_rp8 on + # x1 + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" + end + device ref pcie_rp9 on + # x4 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + end + device ref pcie_rp13 on + register "PcieRpEnable[12]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + register "PcieRpClkReqNumber[12]" = "1" + end device ref uart0 on end device ref uart1 on end device ref gspi0 on end -- cgit v1.2.3