From 55e5cb8d4e116d70c69ca5e91f4afdbffe0d5866 Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Wed, 30 Oct 2019 10:14:23 +0800 Subject: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config This patch enables lockdown configuration for saddlebrook platform BUG=None TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold, resume boot path's. Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/36451 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/intel/saddlebrook/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/intel/saddlebrook') diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 385a4be19f..7d7b58bd34 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,6 +61,11 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | -- cgit v1.2.3