From 6ebb3b60a451b094376ddeff1c3b7b405190f62d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 18 Dec 2021 13:16:06 +0100 Subject: mainboard: Fix comment about early GPIOs These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Felix Singer Reviewed-by: Sean Rhodes Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- src/mainboard/intel/saddlebrook/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel/saddlebrook/gpio.h') diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index f60515b8ec..b012462875 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -245,7 +245,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock. */ static const struct pad_config early_gpio_table[] = { /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ }; -- cgit v1.2.3