From 91dfb920383a8761711e1312f2bcffd2f9529dfb Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 25 Jul 2020 14:01:52 +0200 Subject: soc/intel/skylake: Enable HECI3 depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HECI3 controller. I checked all corresponding mainboards if the devicetree configuration matches the Heci3Enabled setting. Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/intel/saddlebrook/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/intel/saddlebrook/devicetree.cb') diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 944cb50c33..a8066d5cb2 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" -- cgit v1.2.3