From 4dee7b528d3d85ffcca9b7f1fe02959e4113e106 Mon Sep 17 00:00:00 2001 From: Teo Boon Tiong Date: Thu, 7 Sep 2017 00:48:55 +0800 Subject: mainboard/intel/saddlebrook: add support for Saddle Brook Add initial files to support the Saddle Brook board. This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. Most of the code has been taken carried over from kunimitsu with changes done for Saddle Brook. Saddle Brook is a reference board for Skylake SOC and has DDR4. TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully. Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Signed-off-by: Anuj Mittal Signed-off-by: Teo Boon Tiong Reviewed-on: https://review.coreboot.org/21436 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/intel/saddlebrook/bootblock.c | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 src/mainboard/intel/saddlebrook/bootblock.c (limited to 'src/mainboard/intel/saddlebrook/bootblock.c') diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c new file mode 100644 index 0000000000..cf9740db80 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "gpio.h" + +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- cgit v1.2.3