From 453805ceb948b1a8de545c4547b38bb45b5206ed Mon Sep 17 00:00:00 2001 From: Harsha B R Date: Sat, 4 Feb 2023 10:35:50 +0530 Subject: mb/intel/mtlrvp: Enable PCIe port 8 for WLAN This patch enables PCIe port for WLAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets is enumerated as part of lspci in AP console. ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE Advanced Modem (rev 01) Signed-off-by: Harsha B R Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74 Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778 Reviewed-by: Eric Lai Reviewed-by: Sridhar Siricilla Tested-by: build bot (Jenkins) --- .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/intel/mtlrvp') diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 1573cdffbb..53464f91b5 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -87,6 +87,14 @@ chip soc/intel/meteorlake .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, }" end # WWAN + device ref pcie_rp8 on + # Enable PCH PCIE RP 8 using CLK 5 + register "pcie_rp[PCIE_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, + }" + end # WLAN device ref pcie_rp10 on # Enable SSD Gen4 PCIE 10 using CLK 8 register "pcie_rp[PCIE_RP(10)]" = "{ -- cgit v1.2.3