From 8894a55fc830683a09ec1eae813a24180b275d7f Mon Sep 17 00:00:00 2001 From: Ashish Kumar Mishra Date: Thu, 17 Nov 2022 14:48:26 +0530 Subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: Eric Lai --- src/mainboard/intel/mtlrvp/spd/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/mainboard/intel/mtlrvp/spd/Makefile.inc (limited to 'src/mainboard/intel/mtlrvp/spd') diff --git a/src/mainboard/intel/mtlrvp/spd/Makefile.inc b/src/mainboard/intel/mtlrvp/spd/Makefile.inc new file mode 100644 index 0000000000..be4d98bd1d --- /dev/null +++ b/src/mainboard/intel/mtlrvp/spd/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## + +ifneq ($(SPD_SOURCES),) +LIB_SPD_DEPS := $(SPD_SOURCES) +endif -- cgit v1.2.3