From 264566c177dac98e67c2a4765fe08c5d8de10753 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 15:06:48 -0600 Subject: Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/intel/mtarvon/Kconfig | 29 -------- src/mainboard/intel/mtarvon/Kconfig.name | 2 - src/mainboard/intel/mtarvon/board_info.txt | 1 - src/mainboard/intel/mtarvon/devicetree.cb | 45 ------------ src/mainboard/intel/mtarvon/irq_tables.c | 39 ---------- src/mainboard/intel/mtarvon/mptable.c | 107 --------------------------- src/mainboard/intel/mtarvon/romstage.c | 114 ----------------------------- 7 files changed, 337 deletions(-) delete mode 100644 src/mainboard/intel/mtarvon/Kconfig delete mode 100644 src/mainboard/intel/mtarvon/Kconfig.name delete mode 100644 src/mainboard/intel/mtarvon/board_info.txt delete mode 100644 src/mainboard/intel/mtarvon/devicetree.cb delete mode 100644 src/mainboard/intel/mtarvon/irq_tables.c delete mode 100644 src/mainboard/intel/mtarvon/mptable.c delete mode 100644 src/mainboard/intel/mtarvon/romstage.c (limited to 'src/mainboard/intel/mtarvon') diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig deleted file mode 100644 index 11c26261c9..0000000000 --- a/src/mainboard/intel/mtarvon/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -if BOARD_INTEL_MTARVON - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_MPGA479M - select NORTHBRIDGE_INTEL_I3100 - select SOUTHBRIDGE_INTEL_I3100 - select SUPERIO_INTEL_I3100 - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - -config MAINBOARD_DIR - string - default intel/mtarvon - -config MAINBOARD_PART_NUMBER - string - default "3100 devkit (Mt. Arvon)" - -config IRQ_SLOT_COUNT - int - default 1 - -config MAX_CPUS - int - default 4 - -endif # BOARD_INTEL_MTARVON diff --git a/src/mainboard/intel/mtarvon/Kconfig.name b/src/mainboard/intel/mtarvon/Kconfig.name deleted file mode 100644 index 30b547e28f..0000000000 --- a/src/mainboard/intel/mtarvon/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_MTARVON - bool "3100 devkit (Mt. Arvon)" diff --git a/src/mainboard/intel/mtarvon/board_info.txt b/src/mainboard/intel/mtarvon/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/intel/mtarvon/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb deleted file mode 100644 index c1ff1d585a..0000000000 --- a/src/mainboard/intel/mtarvon/devicetree.cb +++ /dev/null @@ -1,45 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA479M - device lapic 0 on end - end - end -end diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c deleted file mode 100644 index 958b2d389b..0000000000 --- a/src/mainboard/intel/mtarvon/irq_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ - 0x0000, /* u16 reserve IRQ for PCI */ - 0x8086, /* u16 Vendor */ - 0x2670, /* Device ID */ - 0x00000000, /* u32 miniport_data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x49, /* u8 checksum - mod 256 checksum must give zero */ - { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c deleted file mode 100644 index ee9d1c28f2..0000000000 --- a/src/mainboard/intel/mtarvon/mptable.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This code is based on src/mainboard/intel/jarrell/mptable.c */ - -#include -#include -#include -#include -#include -#include - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 bus_pci = 6; - u8 bus_pcie_a = 1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR); - - mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0); - - /* Standard local interrupt assignments */ - mptable_lintsrc(mc, bus_isa); - - /* Internal PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */ - - /* PCI slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x00, 0x01, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x01, 0x01, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x02, 0x01, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x03, 0x01, 0x13); - - /* PCIe port A slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x00, 0x01, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x01, 0x01, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x02, 0x01, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x03, 0x01, 0x13); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c deleted file mode 100644 index 13f425e1cf..0000000000 --- a/src/mainboard/intel/mtarvon/romstage.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include -#include -#include "northbridge/intel/i3100/memory_initialized.c" -#include -#include -#include - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i3100/raminit.c" -#include "lib/generic_sdram.c" -#if 0 /* skip_romstage doesn't compile with gcc */ -#include "arch/x86/lib/stages.c" -#endif - -void mainboard_romstage_entry(unsigned long bist) -{ - msr_t msr; - u16 perf; - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, - .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, - } - }; - - if (bist == 0) { -#if 0 /* skip_romstage doesn't compile with gcc */ - /* Skip this if there was a built in self test failure */ - if (memory_initialized()) { - skip_romstage(); - } -#endif - } - - /* Set up the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* print_pci_devices(); */ - enable_smbus(); - /* dump_spd_registers(); */ - - /* Enable SpeedStep and automatic thermal throttling */ - /* FIXME: move to Pentium M init code */ - msr = rdmsr(0x1a0); - msr.lo |= (1 << 3) | (1 << 16); - wrmsr(0x1a0, msr); - msr = rdmsr(0x19d); - msr.lo |= (1 << 16); - wrmsr(0x19d, msr); - - /* Set CPU frequency/voltage to maximum */ - /* FIXME: move to Pentium M init code */ - msr = rdmsr(IA32_PERF_STATUS); - perf = msr.hi & 0xffff; - msr = rdmsr(0x199); - msr.lo &= 0xffff0000; - msr.lo |= perf; - wrmsr(0x199, msr); - - sdram_initialize(ARRAY_SIZE(mch), mch); - /* dump_pci_devices(); */ - /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ - /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ -} -- cgit v1.2.3