From 58562405c8c416a415652516b8af31b204b4ff0d Mon Sep 17 00:00:00 2001
From: Martin Roth <martinroth@google.com>
Date: Sun, 11 Oct 2015 10:36:26 +0200
Subject: Revert "Remove FSP Rangeley SOC and mohonpeak board support"

This chip is still being used and should not have been deleted.  It's
a current intel chip, and doesn't even require an ME binary.

This reverts commit 959478a763c16688d43752adbae2c76e7764da45.

Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/intel/mohonpeak/dsdt.asl | 53 ++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 src/mainboard/intel/mohonpeak/dsdt.asl

(limited to 'src/mainboard/intel/mohonpeak/dsdt.asl')

diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl
new file mode 100644
index 0000000000..c44d56f21a
--- /dev/null
+++ b/src/mainboard/intel/mohonpeak/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Include debug methods
+	#include <arch/x86/acpi/debug.asl>
+
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
+
+	#include "acpi/thermal.asl"
+
+	#include <cpu/intel/fsp_model_406dx/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
+			#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl>
+}
-- 
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