From 2c482a969a546a70c2787d4d96d1ac212da11eff Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 7 Sep 2015 01:54:23 -0700 Subject: intel: Do not hardcode the position of mrc.cache The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/mainboard/intel/minnowmax/Kconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/mainboard/intel/minnowmax') diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 636972f604..39f84f125f 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -49,11 +49,6 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" -config MRC_CACHE_LOC - hex - default 0xfff80000 - depends on ENABLE_FSP_FAST_BOOT - config CBFS_SIZE hex default 0x00300000 -- cgit v1.2.3