From 35f03d902700e5a9d99a561516588169598b0f07 Mon Sep 17 00:00:00 2001
From: Brenton Dong <brenton.m.dong@intel.com>
Date: Mon, 6 Feb 2017 16:07:27 -0700
Subject: mainboard/intel: Add MinnowBoard 3

This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.

This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.

Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/intel/minnow3/dsdt.asl | 42 ++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 src/mainboard/intel/minnow3/dsdt.asl

(limited to 'src/mainboard/intel/minnow3/dsdt.asl')

diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl
new file mode 100644
index 0000000000..004523a0ff
--- /dev/null
+++ b/src/mainboard/intel/minnow3/dsdt.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <soc/intel/apollolake/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/apollolake/acpi/northbridge.asl>
+			#include <soc/intel/apollolake/acpi/southbridge.asl>
+			#include <soc/intel/apollolake/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/apollolake/acpi/sleepstates.asl>
+}
-- 
cgit v1.2.3