From 9586dc72dbd61b56975dd4c24793ef1cdc2d012b Mon Sep 17 00:00:00 2001 From: Marcin Wojciechowski Date: Fri, 20 Nov 2015 14:53:46 +0100 Subject: mainboard/intel: Add Little Plains This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/littleplains/devicetree.cb | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 src/mainboard/intel/littleplains/devicetree.cb (limited to 'src/mainboard/intel/littleplains/devicetree.cb') diff --git a/src/mainboard/intel/littleplains/devicetree.cb b/src/mainboard/intel/littleplains/devicetree.cb new file mode 100644 index 0000000000..1df54d395c --- /dev/null +++ b/src/mainboard/intel/littleplains/devicetree.cb @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/intel/fsp_rangeley + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/fsp_model_406dx + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 1.0 on end # PCIe Port #1 + device pci 2.0 on end # PCIe Port #2 + device pci 3.0 on end # PCIe Port #3 + device pci 4.0 on end # PCIe Port #4 + chip southbridge/intel/fsp_rangeley # Rangeley SB + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x0f" + + register "fadt_pm_profile" = "PM_DESKTOP" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + device pci 0b.0 on end # IQIA + device pci 0e.0 on end # RAS + device pci 13.0 on end # SMBus 1 + device pci 14.0 on end # GbE 0 + device pci 14.1 on end # GbE 1 + device pci 14.2 on end # GbE 2 + device pci 14.3 on end # GbE 3 + device pci 16.0 on end # USB EHCI + device pci 17.0 on end # SATA 2.0 + device pci 18.0 on end # SATA 3.0 + device pci 1f.0 on end # LPC bridge + device pci 1f.3 on end # SMBus 0 + end + end +end -- cgit v1.2.3