From 5c56ce13f4a81970ed8c9a2987c2ea55376da52d Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Wed, 15 Jul 2015 16:02:25 +0530 Subject: Skylake: Only support UART2 as debug port, clean up the rest On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Wenkai Du Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/intel/kunimitsu/Kconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/mainboard/intel/kunimitsu/Kconfig') diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 8971d71286..78d40818ea 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select INTEL_PCH_UART_CONSOLE select LID_SWITCH select MAINBOARD_HAS_CHROMEOS select MARK_GRAPHICS_MEM_WRCOMB @@ -33,10 +32,6 @@ config BOOT_MEDIA_SPI_BUS int default 0 -config INTEL_PCH_UART_CONSOLE_NUMBER - hex - default 2 - config MAINBOARD_DIR string default "intel/kunimitsu" -- cgit v1.2.3