From 576f1cd44b89c0436332200ca35ccd9f9bb54815 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 21:39:55 +0200 Subject: skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Tested-by: build bot (Jenkins) --- src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 6 ++---- src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 5 ++--- src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb | 5 ++--- 3 files changed, 6 insertions(+), 10 deletions(-) (limited to 'src/mainboard/intel/kblrvp') diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 8a3161a41f..9d4c0d9286 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -41,10 +41,6 @@ chip soc/intel/skylake # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - # USB related - register "SsicPortEnable" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -66,6 +62,8 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 0af8282659..7de1454cca 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -71,9 +71,6 @@ chip soc/intel/skylake # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -91,6 +88,8 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 010312c4d4..eb13212a57 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -93,9 +93,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[16]" = "7" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -118,6 +115,8 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ [1] = USB2_PORT_MAX(OC5), /* Front panel */ -- cgit v1.2.3