From 4fa8a6f4fefe04eaa1579c03d36abf0fbc9a27f7 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 14 Mar 2017 16:37:55 -0700 Subject: intel/skylake: Fix bug in VR configuration with FSP 2.0 With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../intel/kblrvp/variants/rvp7/devicetree.cb | 40 ++++++++-------------- 1 file changed, 14 insertions(+), 26 deletions(-) (limited to 'src/mainboard/intel/kblrvp/variants/rvp7') diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index e79c046b8f..369629263b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -65,20 +65,20 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ @@ -104,18 +104,6 @@ chip soc/intel/skylake .icc_max = 0x0, \ .voltage_limit = 0x0 \ }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 0x0, \ - }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ -- cgit v1.2.3