From e7fb7ce06577d88a193c8553b2d94c12eb256c58 Mon Sep 17 00:00:00 2001 From: Divya Chellap Date: Tue, 19 Dec 2017 20:16:50 +0530 Subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/intel/kblrvp/variants/rvp3') diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index 0d2bd0f397..a8e835e95c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -138,16 +138,22 @@ chip soc/intel/skylake register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" + # RP1, uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" + # RP5, uses uses CLK SRC 3 + register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" + # RP6, uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" # PCIE Port 7 Disabled # PCIE Port 8 Disabled @@ -155,11 +161,15 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" + # RP9, uses uses CLK SRC 5 + register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" + # RP10, uses uses CLK SRC 4 + register "PcieRpClkSrcNumber[9]" = "4" # USB 2.0 Enable all ports register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port -- cgit v1.2.3