From cc93db94351a0abb7ae4d8d3fd70209e31f830e1 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 23 Oct 2023 16:26:20 +0200 Subject: mb/intel/skylake/devicetree: Use comma separated list for arrays In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified lines. Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- .../intel/kblrvp/variants/rvp3/overridetree.cb | 36 ++++++++++++---------- 1 file changed, 19 insertions(+), 17 deletions(-) (limited to 'src/mainboard/intel/kblrvp/variants/rvp3') diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 27652d0fe5..4a1c67b94a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -74,24 +74,26 @@ chip soc/intel/skylake # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port - register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" - # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN -- cgit v1.2.3