From ab5d6902fdef7c7f26145619030a42aeda24b1ab Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Sat, 15 Oct 2016 18:13:55 +0530 Subject: mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3 Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/kblrvp/mainboard.c | 109 +++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 src/mainboard/intel/kblrvp/mainboard.c (limited to 'src/mainboard/intel/kblrvp/mainboard.c') diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c new file mode 100644 index 0000000000..fe4fb3ab24 --- /dev/null +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ec.h" +#include "gpio.h" + +static const char *oem_id_maxim = "INTEL"; +static const char *oem_table_id_maxim = "SCRDMAX"; + +static void mainboard_init(device_t dev) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +static uint8_t select_audio_codec(void) +{ + int audio_db_sel = gpio_get(AUDIO_DB_ID); + + return audio_db_sel; +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + + if (select_audio_codec()) { + /* ADI Smart Amps for left and right. */ + if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add ssm4567.\n"); + } else { + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add max98357.\n"); + + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + } + + /* NAU88l25 Headset codec. */ + if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- cgit v1.2.3