From f04e83abbf98d1d55ec2c4fea3fb74bf2f459139 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 19:00:00 +0000 Subject: soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/jasperlake_rvp/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/intel/jasperlake_rvp') diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index a5b5c39fd4..2d72f95077 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -33,6 +33,9 @@ config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC if BOARD_INTEL_JASPERLAKE_RVP_COMMON +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "intel/jasperlake_rvp" -- cgit v1.2.3