From da968d5f2eb702aecc8374a36faa7dc583e15f7f Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 6 Apr 2020 16:37:01 +0530 Subject: mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP Enable S0ix from devicetree for JSLRVP TEST= Build, boot JSLRVP and Verified S0ix is working by running "echo freeze > /sys/power/state" from kernel console. Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Paul Menzel Reviewed-by: V Sowmya --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel/jasperlake_rvp') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 76ad831e4c..e8fc451661 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -124,7 +124,7 @@ chip soc/intel/jasperlake register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "0" + register "s0ix_enable" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, -- cgit v1.2.3