From 2fd49721b17f9020c2b449aad778f011dae7bf46 Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Mon, 16 Dec 2019 23:41:36 -0800 Subject: soc/intel/tigerlake: Update chip files Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/intel/jasperlake_rvp') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index b4ed69744b..854df4656b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -8,9 +8,9 @@ chip soc/intel/tigerlake # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration register "SaGv" = "SaGv_Enabled" -- cgit v1.2.3