From 2f2c7ebfb4059220179cd16e2c7d0f422fbe5841 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 2 Jan 2020 16:11:27 -0800 Subject: soc/intel/tigerlake: Enable Audio on TGL Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Wonkyu Kim --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel/jasperlake_rvp') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fb636251da..843de142b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/tigerlake register "gen3_dec" = "0x00fc0901" register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkHdaEnable" = "1" # PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" -- cgit v1.2.3