From a15eaec1e6975d78687aaea06996464b5a67f14c Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Mon, 27 Apr 2020 22:53:40 +0530 Subject: mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: V Sowmya Reviewed-by: Ronak Kanabar Reviewed-by: Maulik V Vaghela --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mainboard/intel/jasperlake_rvp/variants') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index cb3d1f3598..1b5e256de7 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -67,8 +67,17 @@ chip soc/intel/jasperlake register "PcieRpEnable[1]" = "1" register "PcieRpEnable[4]" = "1" + # Enable ClkReqDetect 1 for WLAN + # Enable ClkReqDetect 4 for NVMe + register "PcieRpClkReqDetect[1]" = "1" + register "PcieRpClkReqDetect[4]" = "1" + register "PcieClkSrcUsage[0]" = "0x04" register "PcieClkSrcUsage[1]" = "0x01" + register "PcieClkSrcUsage[2]" = "0xFF" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcClkReq[0]" = "0x00" register "PcieClkSrcClkReq[1]" = "0x01" -- cgit v1.2.3