From ccbe5307d80c28953132a02dae97f0a984ffecbc Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 11 Sep 2020 18:51:36 +0530 Subject: soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN Enable processor thermal control using PCI dev path function instead of Device4Enable parameter in devicetree. This change removes the dependency on Device4Enable in devicetree. We can enable and disable this thermal control using on and off support with PCI device entry in devicetree. BRANCH=None BUG=None TEST=Built and tested on dedede board Change-Id: I0463236996ad001af506c9966840b27fe44d60d2 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 035ccbd301..f8fea47aa5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -128,9 +128,6 @@ chip soc/intel/jasperlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config" = "{ .tdp_pl1_override = 6, -- cgit v1.2.3