From 630aa4b3db1b7fa459380ec52328d632b53b22de Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:19:19 +0530 Subject: mb/intel/jasperlake_rvp: Add initial mainboard code This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Jasperlake". 2. Replace "icelake_rvp" with "jasperlake_rvp". 3. Rename "icl" with "jsl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake" as tigerlake SOC hosts jasperlake code as well. 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC 10. Replace icl_u and icl_y variant with jslrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per jasperlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 10MB BIOS region. TEST=Build jasperlake rvp board Change-Id: I3314215807959b7348b71933fbba98e6487c0632 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/mainboard/intel/jasperlake_rvp/bootblock.c | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 src/mainboard/intel/jasperlake_rvp/bootblock.c (limited to 'src/mainboard/intel/jasperlake_rvp/bootblock.c') diff --git a/src/mainboard/intel/jasperlake_rvp/bootblock.c b/src/mainboard/intel/jasperlake_rvp/bootblock.c new file mode 100644 index 0000000000..01b257cf9e --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} -- cgit v1.2.3