From faf7a8e8592f47dc9c92ab1672e30bbf60bc3581 Mon Sep 17 00:00:00 2001
From: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Date: Wed, 2 Aug 2017 18:51:47 +0200
Subject: mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB

The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.

Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
---
 src/mainboard/intel/harcuvar/dsdt.asl | 53 +++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 src/mainboard/intel/harcuvar/dsdt.asl

(limited to 'src/mainboard/intel/harcuvar/dsdt.asl')

diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl
new file mode 100644
index 0000000000..4e66d179bb
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// Thermal Handler
+	#include "acpi/thermal.asl"
+
+	// global NVS and variables
+	#include <soc/intel/denverton_ns/acpi/globalnvs.asl>
+
+	#include <soc/intel/denverton_ns/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/denverton_ns/acpi/northcluster.asl>
+			#include <soc/intel/denverton_ns/acpi/southcluster.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/denverton_ns/acpi/sleepstates.asl>
+}
-- 
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