From faf7a8e8592f47dc9c92ab1672e30bbf60bc3581 Mon Sep 17 00:00:00 2001 From: Mariusz Szafranski Date: Wed, 2 Aug 2017 18:51:47 +0200 Subject: mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC ("Denverton" and "Denverton-NS") for the communications segment/market. The MohonPeak coreboot was used as the starting template with additions/modifications from other Intel Apollo Lake/Skylake coreboot. Tested with TianoCore payload (UDK2015) and Poky (Yocto Project Reference Distro) 2.0 with kernel 4.1.8 booted from SATA drive and external USB pendrive. Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a Signed-off-by: Mariusz Szafranski Reviewed-on: https://review.coreboot.org/20862 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG --- src/mainboard/intel/harcuvar/Kconfig | 49 ++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 src/mainboard/intel/harcuvar/Kconfig (limited to 'src/mainboard/intel/harcuvar/Kconfig') diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig new file mode 100644 index 0000000000..9d43b11e07 --- /dev/null +++ b/src/mainboard/intel/harcuvar/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 - 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_HARCUVAR + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_DENVERTON_NS + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/harcuvar + +config MAINBOARD_PART_NUMBER + string + default "Harcuvar CRB" + +config MAINBOARD_VENDOR + string + default "Intel" + +config ENABLE_FSP_MEMORY_DOWN + bool "Enable Memory Down" + default n + help + Select this option to enable Memory Down function. + +config SPD_LOC + depends on ENABLE_FSP_MEMORY_DOWN + hex "SPD binary location in cbfs" + default 0xfffdf000 + help + Location of SPD binary for memory down function. + +endif # BOARD_INTEL_HARCUVAR -- cgit v1.2.3