From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/intel/glkrvp/boardid.c | 2 +- src/mainboard/intel/glkrvp/ec.c | 4 ++-- src/mainboard/intel/glkrvp/romstage.c | 2 +- src/mainboard/intel/glkrvp/smihandler.c | 8 ++++---- src/mainboard/intel/glkrvp/variants/baseboard/boardid.c | 2 +- src/mainboard/intel/glkrvp/variants/baseboard/gpio.c | 2 +- .../intel/glkrvp/variants/baseboard/include/baseboard/gpio.h | 2 +- src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c | 6 +++--- 8 files changed, 14 insertions(+), 14 deletions(-) (limited to 'src/mainboard/intel/glkrvp') diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 9c5aa6daf7..0676eaca32 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -27,7 +27,7 @@ uint32_t board_id(void) { MAYBE_STATIC int id = -1; if (id < 0) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) id = variant_board_id(); else { if (send_ec_command(EC_FAB_ID_CMD) == 0) diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index 0138a9c234..44b7824224 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -54,7 +54,7 @@ static void bootblock_ec_init(void) void mainboard_ec_init(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (ENV_RAMSTAGE) ramstage_ec_init(); else if (ENV_BOOTBLOCK) @@ -69,7 +69,7 @@ void mainboard_ec_init(void) | LPC_IOE_LGE_200); } - if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) { + if (CONFIG(GLK_INTEL_EC)) { printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n"); outb(0xaa, 0x66); printk(BIOS_INFO, "Hack to turn on the CPU fan\n"); diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c index 8e135903dc..7811d06044 100644 --- a/src/mainboard/intel/glkrvp/romstage.c +++ b/src/mainboard/intel/glkrvp/romstage.c @@ -211,7 +211,7 @@ static void fill_memory_params(FSP_M_CONFIG *cfg) { uint8_t boardid; - if (IS_ENABLED(CONFIG_IS_GLK_RVP_1)) + if (CONFIG(IS_GLK_RVP_1)) boardid = BOARD_ID_GLK_RVP1_DDR4; else boardid = BOARD_ID_GLK_RVP2_LP4; diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c index f6d98e5f20..9af899398f 100644 --- a/src/mainboard/intel/glkrvp/smihandler.c +++ b/src/mainboard/intel/glkrvp/smihandler.c @@ -25,7 +25,7 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) if (gpi_status_get(sts, EC_SMI_GPI)) chromeec_smi_process_events(); } @@ -38,14 +38,14 @@ void mainboard_smi_sleep(u8 slp_typ) pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); return 0; @@ -53,6 +53,6 @@ int mainboard_smi_apmc(u8 apmc) void mainboard_smi_espi_handler(void) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_process_events(); } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c index 8df1dc4c60..69a0a9116a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c @@ -21,7 +21,7 @@ int variant_board_id(void) { MAYBE_STATIC uint32_t id = BOARD_ID_INIT; - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { if (id == BOARD_ID_INIT) { if (google_chromeec_get_board_version(&id)) id = BOARD_ID_UNKNOWN; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 03f2147006..3cbb4bcd44 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */ -#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI) +#if CONFIG(TPM_ON_FAST_SPI) PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */ #endif PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/ diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h index dc23abd2fc..170e87c988 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h @@ -22,7 +22,7 @@ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 * which is North community */ -#if IS_ENABLED(CONFIG_SOC_ESPI) +#if CONFIG(SOC_ESPI) #define EC_SCI_GPI GPE0A_ESPI_SCI_STS #else #define EC_SCI_GPI GPE0_DW1_05 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c index 5433bd571c..c35a2923f5 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c @@ -21,15 +21,15 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { /* 1-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) && + if (CONFIG(NHLT_DMIC_1CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 1)) printk(BIOS_ERR, "Added 1CH DMIC array.\n"); /* 2-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) && + if (CONFIG(NHLT_DMIC_2CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); /* 4-dmic configuration */ - if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) && + if (CONFIG(NHLT_DMIC_4CH_16B) && !nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Added 4CH DMIC array.\n"); -- cgit v1.2.3