From 73f073d393c8cf3064434192fd0237a5ecd30de4 Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Tue, 29 Aug 2017 15:42:27 -0700 Subject: mainboard/intel/glkrvp: Configure Prmrr and Enable SGX Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX by default for GLKRVP platform. Supported PRMRR size options: 0x02000000 - 32MiB 0x04000000 - 64MiB 0x08000000 - 128MiB Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b Signed-off-by: Pratik Prajapati Reviewed-on: https://review.coreboot.org/21278 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/intel/glkrvp/variants') diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index c0831459bd..45badcddbd 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -90,6 +90,14 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + register "sgx_enable" = "1" + + # PRMRR size options + # 0x02000000 - 32MiB + # 0x04000000 - 64MiB + # 0x08000000 - 128MiB + register "PrmrrSize" = "128 * MiB" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3