From cf1ba95fa4daffecaa9d1764163c28e7acf24c6c Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 21 Mar 2018 07:39:40 -0700 Subject: mb/glkrvp: Set PNP config to PNP_PERF_POWER This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Built and booted glkrvp, verified warm and cold reboot and suspend resume. Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/25309 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 5a544300c0..f9ed3cfbff 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -98,6 +98,8 @@ chip soc/intel/apollolake # 0x08000000 - 128MiB register "PrmrrSize" = "128 * MiB" + register "pnp_settings" = "PNP_PERF_POWER" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3