From d59f62bbdabeb98f12896c6af0ef50cbf25e013f Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Fri, 5 May 2017 16:39:21 -0700 Subject: mainboard/intel/glkrvp: Add support for GLKRVP GLKRVP is a reference board for GLK SOC RVP1 has DDR4 and RVP2 has LPDDR4 RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected if building for RVP1 GLKRVP can work with internal Intel EC or external Chrome EC AIC. For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected ( CONFIG_GLK_INTEL_EC should be selected for internal EC config) By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC config. Signed-off-by: Hannah Williams Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Reviewed-on: https://review.coreboot.org/19604 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/glkrvp/ec.c | 80 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 src/mainboard/intel/glkrvp/ec.c (limited to 'src/mainboard/intel/glkrvp/ec.c') diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c new file mode 100644 index 0000000000..7cc2bbbc55 --- /dev/null +++ b/src/mainboard/intel/glkrvp/ec.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void ramstage_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} + +static void bootblock_ec_init(void) +{ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200); + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); +} + +void mainboard_ec_init(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); + } else if (ENV_BOOTBLOCK) + lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | + IOE_LGE_200); + + if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) { + printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n"); + outb(0xaa, 0x66); + } +} -- cgit v1.2.3