From d59f62bbdabeb98f12896c6af0ef50cbf25e013f Mon Sep 17 00:00:00 2001
From: Hannah Williams <hannah.williams@intel.com>
Date: Fri, 5 May 2017 16:39:21 -0700
Subject: mainboard/intel/glkrvp: Add support for GLKRVP

GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1

GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)

By default, CONFIG_GLK_CHROME_EC is selected for  external ChromeEC AIC
config.

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/intel/glkrvp/dsdt.asl | 71 +++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 src/mainboard/intel/glkrvp/dsdt.asl

(limited to 'src/mainboard/intel/glkrvp/dsdt.asl')

diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
new file mode 100644
index 0000000000..9dee22a549
--- /dev/null
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/ec.h>
+#define GPE_EC_WAKE	0x26
+#define EC_SCI_GPI	GPE0_DW1_05
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	/* global NVS and variables */
+	#include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <soc/intel/apollolake/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/apollolake/acpi/northbridge.asl>
+			#include <soc/intel/apollolake/acpi/southbridge.asl>
+			#include <soc/intel/apollolake/acpi/pch_hda.asl>
+		}
+	}
+
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include <variant/acpi/dptf.asl>
+		/* Include soc specific DPTF changes */
+		#include <soc/intel/apollolake/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <soc/intel/common/acpi/dptf/dptf.asl>
+	}
+	#include "touchpad.asl"
+	#include "touchpanel.asl"
+}
-- 
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