From d59f62bbdabeb98f12896c6af0ef50cbf25e013f Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Fri, 5 May 2017 16:39:21 -0700 Subject: mainboard/intel/glkrvp: Add support for GLKRVP GLKRVP is a reference board for GLK SOC RVP1 has DDR4 and RVP2 has LPDDR4 RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected if building for RVP1 GLKRVP can work with internal Intel EC or external Chrome EC AIC. For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected ( CONFIG_GLK_INTEL_EC should be selected for internal EC config) By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC config. Signed-off-by: Hannah Williams Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Reviewed-on: https://review.coreboot.org/19604 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/glkrvp/Makefile.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 src/mainboard/intel/glkrvp/Makefile.inc (limited to 'src/mainboard/intel/glkrvp/Makefile.inc') diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc new file mode 100644 index 0000000000..f2da3794d5 --- /dev/null +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -0,0 +1,20 @@ +bootblock-y += bootblock.c +bootblock-y += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -- cgit v1.2.3