From 93dd5f78ffc7d9f9311866c38afc78062c6a52ef Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Tue, 26 Jan 2016 10:06:42 -0800 Subject: mainboard/intel/galileo: Add Intel Galileo Gen 2 Support Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/galileo/devicetree.cb | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 src/mainboard/intel/galileo/devicetree.cb (limited to 'src/mainboard/intel/galileo/devicetree.cb') diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100644 index 0000000000..ab4f246fda --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end -- cgit v1.2.3