From 2198c583b258d5f8bb20a1f5411391a4ee4d4c83 Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <reinauer@chromium.org>
Date: Thu, 7 Jun 2012 15:38:44 -0700
Subject: Move GGL0001 ACPI code to generic ChromeOS code

The only difference in this code on all our platforms is the array
describing the GPIOs. Hence, only keep that array in the mainboard
ChromeOS directory and move everything else to generic ChromeOS ACPI
code.

Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
---
 src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 100 ++-------------------
 src/mainboard/intel/emeraldlake2/dsdt.asl          |   1 +
 2 files changed, 6 insertions(+), 95 deletions(-)

(limited to 'src/mainboard/intel/emeraldlake2')

diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
index 6a61b0d912..307e2e2cd9 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
@@ -17,98 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-Device (CRHW)
-{
-	Name(_HID, EISAID("GGL0001"))
-
-	Method(_STA, 0, Serialized)
-	{
-		Return (0xb)
-	}
-
-	Method(CHSW, 0, Serialized)
-	{
-		Name (WSHC, Package() { VBT3 })
-		Return (WSHC)
-	}
-
-	Method(FWID, 0, Serialized)
-	{
-		Name (DIW1, "")
-		ToString(VBT5, 63, DIW1)
-		Name (DIWF, Package() { DIW1 })
-		Return(DIWF)
-	}
-
-	Method(FRID, 0, Serialized)
-	{
-		Name (DIR1, "")
-		ToString(VBT6, 63, DIR1)
-		Name (DIRF, Package() { DIR1 })
-		Return (DIRF)
-	}
-
-	Method(HWID, 0, Serialized)
-	{
-		Name (DIW0, "")
-		ToString(VBT4, 255, DIW0)
-		Name (DIWH, Package() { DIW0 })
-		Return (DIWH)
-	}
-
-	Method(BINF, 0, Serialized)
-	{
-		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
-		Return (FNIB)
-	}
-
-	Method(GPIO, 0, Serialized)
-	{
-		Name(OIPG, Package() {
-			Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
-			Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
-			Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
-		})
-		Return (OIPG)
-
-	}
-
-	Method(VBNV, 0, Serialized)
-	{
-		Name(VNBV, Package() {
-			// See src/vendorcode/google/chromeos/Kconfig
-			// for the definition of these:
-			CONFIG_VBNV_OFFSET,
-			CONFIG_VBNV_SIZE
-		})
-		Return(VNBV)
-	}
-
-	Method(VDAT, 0, Serialized)
-	{
-		Name(TAD0,"")
-		ToBuffer(CHVD, TAD0)
-		Name (TADV, Package() { TAD0 })
-		Return (TADV)
-	}
-
-	Method(FMAP, 0, Serialized)
-	{
-		Name(PAMF, Package() { VBT9 })
-		Return(PAMF)
-	}
-
-	Method(MECK, 0, Serialized)
-	{
-		Name(HASH, Package() { MEHH })
-		Return(HASH)
-	}
-
-	Method(MLST, 0, Serialized)
-	{
-		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
-			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
-		})
-		Return (TSLM)
-	}
-}
+Name(OIPG, Package() {
+	Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
+	Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
+	Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index 9af312ab09..b67082e721 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -49,6 +49,7 @@ DefinitionBlock(
 	}
 
 	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */
 	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
-- 
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