From 6beaef983aee5d886f6f8571855a92d608d98a17 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Jun 2019 23:29:23 +0200 Subject: sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Patrick Rudolph --- src/mainboard/intel/emeraldlake2/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/emeraldlake2/devicetree.cb') diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 60072b0995..4ed1f3c694 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -44,8 +44,11 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" + register "gen1_dec" = "0x00fc1601" + # runtime_port registers + register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen3_dec" = "0x003c0701" register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" -- cgit v1.2.3