From b0f81518b5c17466bc95ebdef292e82c4b76bc88 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Mon, 25 Jul 2016 21:31:41 -0500
Subject: chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/mainboard/intel/emeraldlake2/chromeos.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/mainboard/intel/emeraldlake2/chromeos.c')

diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index bb4ebe9f54..896f8767f8 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -91,3 +92,14 @@ int get_recovery_mode_switch(void)
 	/* Recovery: GPIO22, active low */
 	return !get_gpio(22);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
-- 
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